Key takeaways
- A U.S.-designed AI accelerator typically depends on fabrication in Taiwan, high-bandwidth memory largely from South Korea, and packaging and assembly across Asia.
- HBM stacks memory dies next to the processor to keep GPUs supplied with data; its supply is concentrated in SK hynix, Samsung and Micron.
- NVIDIA designs its chips but relies on foundries, chiefly TSMC, to manufacture them; that efficiency also creates concentration risk.
- Advanced packaging such as TSMC's CoWoS has become part of the computing architecture and can be a bottleneck just like wafer capacity.
- New U.S. fabs and packaging plants add resilience, but complete independence is unrealistic; diversified, allied supply is the practical goal.
When we talk about commercializing AI in the United States, we naturally focus on the companies at the front of the pack. NVIDIA dominates much of the AI accelerator market. OpenAI has become almost synonymous with generative AI. Google, Microsoft, Meta and Amazon are spending extraordinary sums on models, cloud infrastructure and, increasingly, their own custom AI processors. Looking at that list, it is easy to conclude that the United States controls the AI technology stack.
That is only half the story. Underneath the software platforms, models and GPU architectures sits an extremely complex global manufacturing ecosystem, much of it outside the United States, and some of its most important pieces are concentrated in a handful of companies and locations. A cutting-edge GPU designed in California may depend on chip fabrication in Taiwan, high-bandwidth memory made largely in South Korea, substrates and packaging from Asian suppliers, and assembly through a network of manufacturers across several countries. An AI chip is no longer simply a chip; it is an integrated computing system assembled from some of the most advanced technologies the semiconductor industry has produced.
Understanding the real scale of the AI era therefore means looking beyond Silicon Valley, at the partnerships and dependencies that make its innovation possible. Three parts of that ecosystem deserve particular attention because they show where the next hardware bottlenecks may appear: high-bandwidth memory, leading-edge fabrication and advanced packaging.
The GPU Is Only One Part of the Machine
For many people, NVIDIA's GPU is the physical symbol of AI, and for good reason. GPUs perform the massive volumes of parallel calculations needed to train and run large models, and when hyperscalers describe clusters of tens or hundreds of thousands of accelerators, GPUs dominate the conversation. But focusing only on the processor misses how AI hardware actually works.
The processor has to move enormous amounts of data continuously. AI models contain billions or trillions of parameters that must shuttle between memory and the GPU's computing cores at extraordinary speed. If the processor sits waiting for data, much of its expensive capacity is wasted. That is why one of the least glamorous components in the system has become one of the industry's most strategic technologies: high-bandwidth memory, or HBM.
HBM: The Memory AI Cannot Easily Live Without
Conventional computer memory is mounted on a circuit board some distance from the processor, which works well for most computing. AI accelerators are different. The volume of data flowing between processor and memory is so large that conventional layouts create a traffic jam, and even a very fast processor delivers limited value if its data arrives too slowly.
HBM approaches the problem differently. Instead of spreading memory chips across a board, it stacks multiple DRAM dies vertically, with tiny connections running through the stack, so data can travel through a very wide interface placed right next to the processor. Think of it as replacing a crowded two-lane road with a wide highway running directly into the GPU.
The technology is advancing quickly. The move from HBM3 and HBM3E to HBM4 doubled the interface width; Micron's HBM4, for example, uses a 2,048-bit interface and delivers more than 2.8 terabytes per second of bandwidth per stack. NVIDIA's Rubin architecture uses HBM4 and is specified with up to 288 GB of HBM and roughly 22 TB/s of memory bandwidth per GPU, a key enabler of larger models, longer context windows and more complex reasoning workloads. The GPU performs the calculations; HBM keeps it fed. That makes memory manufacturers strategic players in AI.
A highly concentrated supply chain
Here geography becomes important. The world's leading HBM suppliers are SK hynix, Samsung Electronics and Micron, and two of the three are South Korean. SK hynix has become particularly important; Reuters has reported that it holds a majority share of the global HBM market and plans to double its wafer capacity over the next five years. Samsung is expanding its HBM business rapidly, while U.S.-based Micron has become an important supplier and has entered volume production of HBM4 for NVIDIA's Vera Rubin platform. SK hynix began mass shipments of HBM4 in the second quarter of 2026 and is preparing HBM4E for future systems.
This is a crucial point: the growth of AI computing capacity is limited not only by how many GPUs can be designed but by how much HBM the memory industry can manufacture, test and package. HBM is hard to make because multiple DRAM dies must be produced at high yield, thinned, stacked, interconnected and thermally managed, and a defect in one layer can ruin an expensive finished device. As stacks get taller and bandwidth targets rise, manufacturing gets harder still. That explains why HBM capacity is so valuable, and why NVIDIA and SK hynix have extended their collaboration on future memory generations well beyond ordinary purchasing. Memory has moved from a commodity attached to a processor to part of the processor's strategic architecture.
The Second Dependency: Who Manufactures the GPU?
NVIDIA is one of the world's most sophisticated semiconductor companies, but it is fundamentally a chip designer. It does not operate the leading-edge fabs needed to manufacture its most advanced processors. That distinction sits at the center of the modern industry. Designing a state-of-the-art AI processor requires extraordinary intellectual property; manufacturing it requires an entirely different set of capabilities, including extreme ultraviolet lithography, atomic-scale process control, advanced materials, thousands of process steps and enormous capital investment.
Only a few companies can manufacture logic chips at the most advanced nodes, and Taiwan Semiconductor Manufacturing Company (TSMC) occupies an unusually important position among them. Its AI and high-performance computing customers include NVIDIA, AMD, Google, Amazon, Meta and Microsoft. For American AI companies, this creates a distinctive arrangement: much of the architectural innovation originates in the United States, while much of the manufacturing expertise resides in Taiwan.
That relationship has been enormously successful. The foundry model let companies like NVIDIA concentrate their resources on architecture and software instead of also building fabs that cost tens of billions of dollars. But efficiency creates concentration, and concentration creates risk.
Taiwan has become part of AI infrastructure
Semiconductor manufacturing is often described as a supply-chain issue. For AI, that may understate it: Taiwan's semiconductor ecosystem has become part of the infrastructure of global AI. Beyond TSMC's wafer output, an extensive Taiwanese electronics industry supplies substrates, packaging, testing, motherboards, servers and rack-scale systems. NVIDIA has said its Vera Rubin generation involves hundreds of partners and more than 350 factories in 30 countries, including roughly 150 supply-chain partners in Taiwan. Many of those companies receive far less attention than NVIDIA but are essential to the finished product, from wafer, substrate, packaging and test specialists such as SPIL, Kinsus, KYEC and UMTC to system manufacturers such as Foxconn, Quanta, Wistron, Pegatron and Inventec. Modern AI hardware is not one company, one processor or one factory. It is a manufacturing network.
U.S. manufacturing changes the picture, slowly
The United States clearly recognizes the risk of geographic concentration, and TSMC's Arizona investment is the most visible attempt to rebalance it. TSMC's first Arizona fab began producing 4-nanometer chips in late 2024, and the company has said its second Arizona fab is expected to enter volume production in the second half of 2027. In March 2025 it announced plans to expand its total U.S. investment to $165 billion, including more fabs, advanced packaging facilities and an R&D center.
South Korea's memory industry is moving in the same direction. SK hynix has broken ground on a roughly $4 billion project in Indiana for advanced HBM packaging and R&D, with mass production targeted for 2029. Yet even that project shows how hard it is to localize an entire supply chain: the advanced memory wafers are still expected to be made in South Korea and shipped to Indiana for packaging and testing. Factories can be built relatively quickly. Supply chains, specialized labor, materials networks and decades of manufacturing know-how take much longer to reproduce.
The Third Dependency: Advanced Packaging
Until recently, semiconductor packaging attracted very little public attention. It was often seen as the relatively straightforward final step: fabricate the wafer, cut it into individual dies, and package each die so it could be installed in a system. AI has changed that. Modern accelerators combine large processor dies, multiple chiplets and several HBM stacks in one tightly interconnected package, and those components must communicate at very high bandwidth while controlling latency, power and heat. Packaging is no longer just a protective shell; it has become part of the computing architecture.
Why CoWoS matters
One of the most important technologies in this shift is TSMC's CoWoS (Chip-on-Wafer-on-Substrate) platform. CoWoS places processors and HBM stacks very close together on an advanced interposer, creating thousands of high-speed connections over very short distances. TSMC describes it as a foundational packaging technology for AI and high-performance computing, offered in several generations (CoWoS-S, CoWoS-R and CoWoS-L) that support increasingly large combinations of processors, chiplets and memory.
The physics behind it is simple. Moving data over long distances consumes energy and takes time; moving it a few millimeters inside a package is faster and more efficient. That is why advanced packaging and chip stacking have become so important just as conventional transistor scaling gets harder and more expensive. Instead of expecting every performance gain to come from shrinking transistors, designers can combine specialized chips into sophisticated packages, and TSMC is scaling CoWoS to accommodate larger interposers and more HBM stacks for exactly that reason. The package itself is becoming a miniature computing system.
Packaging capacity can be a bottleneck too
This creates another supply constraint. Even if enough GPU dies are fabricated and enough HBM is produced, the components still have to be integrated, and that requires advanced packaging lines, much of which are again concentrated in Asia. That is why CoWoS capacity was so closely watched during the early AI build-out: producing more accelerators required not only more leading-edge wafers but more packaging capacity.
The industry is responding on several fronts. TSMC continues to expand CoWoS and its other 3DFabric technologies, Intel has developed EMIB and related packaging approaches, Samsung is developing its own integration methods, and outsourced assembly and test companies are moving rapidly up the technology curve. Standards are emerging as well. UCIe (Universal Chiplet Interconnect Express) defines a common way for chiplets to communicate inside a package, and newer versions support 3D packaging and faster die-to-die links. That matters because a future AI processor may not be one large piece of silicon made on one process; it may combine many specialized chiplets made with different technologies and potentially by different suppliers, with the package turning them into one system.
From Transistor Scaling to System Scaling
This may be the most important change in AI hardware. For decades, performance gains came largely from transistor scaling: make transistors smaller, fit more on each chip, and make the chip faster. That formula is becoming much more complicated. Future AI performance will increasingly come from system-level integration, which means processors, HBM, chiplets, substrates, interposers, optical interconnects, networking, power delivery, cooling, packaging and software all have to advance together.
Energy is part of this story. TSMC has discussed how rising AI electricity consumption is pushing the industry to improve performance per watt rather than simply maximize raw compute, with advanced packaging, 3D stacking and photonics at the center of that effort. Every watt saved inside the package reduces the power, cooling and grid capacity a data center needs, which links chip design directly to the grid constraints we cover in articles such as Build It Before They Do.
Interdependence Is Not Only a Weakness
It would be easy to describe America's reliance on foreign semiconductor manufacturing purely as a vulnerability, and real vulnerabilities exist. A major disruption in Taiwan could affect advanced logic production; problems in South Korea could affect HBM supply; shortages of substrates or packaging capacity could slow GPU shipments even if wafers were available. Geopolitics makes those risks impossible to ignore.
But the same ecosystem can be read another way. AI has advanced so quickly precisely because different countries and companies became exceptionally good at different parts of the problem. American companies lead in processor architecture, cloud computing and AI software. Taiwan built a foundry and electronics ecosystem that is extremely difficult to replicate. South Korea developed world-class memory manufacturing. The Netherlands became indispensable in advanced lithography through ASML. Japan remains central in semiconductor materials, chemicals and equipment. Others contribute substrates, testing, precision tools, components and system assembly. AI infrastructure is less an American industrial product than a global technological construction.
The Practical Goal: Resilience, Not Complete Independence
That leads to a practical question: should the United States try to manufacture every critical semiconductor technology domestically? Complete independence sounds attractive but would likely be enormously expensive and unrealistic. A more achievable goal is resilience, which means:
- Expanding U.S. manufacturing in selected strategic areas while keeping strong partnerships with Taiwan, South Korea, Japan, Europe and other allies.
- Having multiple qualified sources of HBM and multiple fabrication locations.
- Supporting more than one advanced packaging platform.
- Diversifying the sources of substrates and critical materials.
- Building enough domestic capacity that a disruption in one region does not halt AI infrastructure construction.
The early signs of that strategy are visible: TSMC is building in Arizona, SK hynix is building advanced memory packaging in Indiana, Micron is expanding HBM production and U.S. memory investment, and Intel continues to push foundry manufacturing and advanced packaging. None of these efforts eliminates the need for the existing Asian ecosystem, and they probably should not try to.
What AI Reveals About Interdependence
There is a certain irony in the current AI race. Governments increasingly frame AI as national competition: who will lead, who will control the technology, who will build the largest models and deploy the most compute. Yet the hardware behind that competition may be one of the most globally interdependent products ever manufactured. An accelerator designed by an American company may contain logic fabricated in Taiwan, memory from a Korean or American producer, interposers and packaging from Asian facilities, lithography equipment from the Netherlands and materials from Japan, and be assembled into systems by yet another network of manufacturers. By the time it reaches a data center in Virginia, Texas or Ohio, it has traveled through a multinational industrial ecosystem.
That is a useful way to think about AI infrastructure. The AI race is not only a race between software companies; it is also a race to expand some of the most difficult manufacturing technologies ever developed, from HBM, leading-edge fabrication and advanced packaging to substrates, lithography, power electronics, networking, cooling and, ultimately, the electrical infrastructure needed to run it all. Recognizing that does not diminish American AI leadership. It explains how that leadership is possible. If we want to understand where AI is going, and where the next supply constraints will emerge, we need to look past the name printed on the GPU to the entire ecosystem that made it.
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Independent analysis of power, grid and policy for AI data centers. Every article lists its sources. About the editor · Editorial policy
